1. Field of the Invention
This invention relates generally to high resistance layers for semiconductors and to methods of manufacturing such layers. The invention has particular utility within the field of high resistance load resistors in static random access memories (SRAMs).
2. Description of the Background Art
This invention produces the most desirable results when applied to the static random access memory, and the following description is directed to the static random access memory.
The static random access memory is well known in the art. There is illustrated in FIG. 11A, an overall arrangement of a conventional 8K word.times.8 bit static random access memory (hereinafter referred to as SRAM). FIG. 11B schematically shows the flow of data in the SRAM of FIG. 11A.
Referring to FIG. 11A, the SRAM includes a memory cell array 41 composed of a plurality of memory cell 40, which constitutes a data storage section. The SRAM also includes an X decoder 42 and a Y decoder 43 coupled to an X address buffer and a Y address buffer, respectively; and an input-output interface section having sense amplifiers connected to output buffers. The plurality of memory cells 40 are arranged at the intersections between the word lines connected to the X decoder 42 and the bit lines connected to the Y decoder, thereby forming the memory cell array 41. In response to externally applied row and column address signals, the X decoder 42 and the Y decoder 43 selects a word line and a bit line, respectively, and a particular memory cell 40 at the intersection between the selected word line and bit line is addressed.
Most specifically, in the address buffer a normal signal X and an inverted signal X are generated in response to the address signal applied thereto. Upon receipt of the signals X and X, the X decoder 42 selects one row of 256 rows of memory cells and charges the word lines coupled to the memory cells in the selected rows to a high level while discharging the remaining word lines to a low level. As a result, the memory cells 40 in the selected row are activated and the data stored in the activated memory cells are supplied to the pairs of bit line and bit line. Of the 32 bit line pairs in each channel, one bit line pair is coupled to the pair of I/O line and I/O line through a multiplexer. The selection in the multiplexer is performed by the Y decoder 43. In this way, the desired 8 bits of memory cells are connected to the I/O line.
In writing data, input data are written into the selected memory cells 40. In reading out data, the data stored in the selected memory cells are sensed and supplied out as the output data by the sense amplifier.
The data writing and reading operations are now described with reference to FIG. 11B. The sense amplifier and a write driver are connected to be I/O line. The data are transferred in the direction of a solid arrow during the read-out operation, while the data are transferred in the direction of a dotted arrow during the writing operation. The write enable or WE signal and the output enable or OE signal, which function like the valves for the controlling the flow of data, regulate the outputs of the word driver and the output buffer, respectively, at a high impedance.
In FIG. 12, there is shown an equivalent circuit for one memory cell 40 in the SRAM of FIG. 11A. The memory cell 40 includes a flip-flop which comprises a pair of driver transistors T1 and T2, (suitably N channel MOSFETs) and pair of load resistors 6 of high resistance value. As shown, the driver transistors T1 and T2 have the gate and drain electrodes cross-coupled, and the load resistors 6 are connected to the drain electrodes of the transistors T1 and T2. Also, connected to the drain electrodes of the transistors T1 an T2 are access transistors T3 and T4 (preferably MOSFETs). The access transistors T3 and T4 have the gate electrodes coupled to the word lines 33. As the word line 33 is selected, the data held in the driver transistors T1 and T2 are transferred to the bit line 31 and bit line 32 through the access transistors T3 and T4.
In operation, when the data stored in the memory cell 40 is to be read out, the word line 33 is activated by the application of a predetermined voltage. As the word lines 33 is activated, it causes voltages corresponding to the present states of the driver transistors T1 and T2 to appear on the bit line 31 and the bit line 32 via the access transistors T3 and T4. When data to be written into the memory cell, the word line 33 is activated by the application of a predetermined voltage. Under the activated conditions, the bit line 31 and bit line 32 are applied with the desired potentials corresponding to the logic state to be written.
Most specifically, when the access transistors T3 and T4 are turned on by the word line 33, the data signals on the bit line 31 and the bit line 32 are latched into the flip-flop composed of the driver transistors T1 and T2. In order to maintain the latched data signal, it is necessary to keep supplying electric current to the flip-flop from a power supply Vcc through the high load resistors 6. In addition, the current supply should preferably be at a possible minimum to keep down the power consumption during the stand-by. However, for the purpose of maintaining the stored data, the supply current must exceed the leakage current of the transistors while being turned off.
Now, the process for manufacturing the conventional memory cell of FIG. 12 is now described with reference to FIGS. 13A-13E which show pattern layouts for the memory cell in successive stages of manufacture.
In FIG. 13A, an oxide isolation layer 2 is selectively formed on the major surface of a P-type silicon substrate 1 to define and isolate active regions 30 yet to be formed.
In FIG. 13B, there are formed gate electrodes 21 and 22, and a word line 33 over the active regions 30 at predetermined positions. And, using the gate electrodes 21 and 22, and the word line 33 as masks, N-type impurity ions are implanted into the active regions 30 to create N.sup.+ diffusion region 3.
In the next step, as shown in FIGS. 13C, a low-resistance polysilicon layer 5 is deposited. The polysilicon layer 5 has a contact 9a between the gate electrode 21 and the N.sup.+ diffusion region 3, a contact 9b to the N.sup.+ diffusion region 3, and a contact 9c between the gate electrode 22 and the N.sup.+ diffusion layers 3. The low-resistance polysilicon layer 5 also includes a high-resistance polysilicon regions 61 and 62 disposed above the gate electrode 21 and 22.
In FIG. 13D, an aluminum interconnection 8 is formed on the low resistance layer 5 and is connected to the layer 5 through a contact 9d formed therein.
Finally as shown in FIG. 13E, contacts 9f and 9e are made in N.sup.+ diffusion regions forming the access transistors T3 and T4. An aluminum interconnection is provided and connect the bit line 31 and bit line 32 through the contacts 9f and 9e, thereby to complete one memory cell.
FIG. 14 shows a partial cross-section of the memory cell taken along the line XIII--XIII of FIG. 13D. Referring now to FIG. 14, fabrication of the high load resistor 6 provided to retain the data latched in the flip-flop composed of the driver transistors T1 and T2 is explained.
As already discussed in connection to FIG. 13C, the high-resistance regions 61 and 62 comprise a high-resistance polysilicon layer. It is noted that the high resistance polysilicon regions normally have a resistance value in the order of several T.OMEGA.. An oxide isolation layer 2 is first deposited on the P-type silicon substrate 1. The gate electrodes of access transistors T3 and T4, and driver transistors T1 and T2 which are shown and represented by a word line 33 in the drawing figure then formed on the silicon substrate with a gate oxide layer 4 interposed between the word lines 33 and the substrate 1. Subsequently, N-type impurity ions such as phosphorous ions and arsenic ions are implanted into the P-type silicon substrate 1 to provide N.sup.+ diffusion regions 3.
Thereafter, undoped polysilicon is deposited and electrically connected to the N.sup.+ diffusion regions 3 by means of direct contact technique. The deposited polysilicon is doped twice with phosphorous ions of different doses thereby to form a low-resistance polysilicon layer 5 and a high-resistance polysilicon layer 61. In other words, the amount of implanted ions in the high resistance polysilicon layer 61 is smaller than that in the low resistance polysilicon layer 5. The large quantity of ions implanted in the low resistance polysilicon layer 5 are diffused into the P-type silicon substrate 1 by a later thermal treatment, creating a highly concentrated N.sup.+ diffusion regions 3.
Finally, an insulation layer 7 is formed, upon which an aluminum interconnection 8 is deposited to be in communication with the low resistance polysilicon layer 5 through the contact 9d. When it is intended to use the low resistance polysilicon layer 5 as the supply line Vcc, the aluminum interconnection can be dispensed with. The high resistance region is provided in this manner.
In FIG. 14, electric current supplied to the aluminum interconnection 8 serving as the power supply line Vcc flows through the low resistance polysilicon layer 5 and the high resistance polysilicon layer 61, and through the direct contact to N.sup.+ diffusion regions 3. The current flows continuous to the ground through the channel regions of the conducting driver transistors T1 and T2.
The conventional SRAM of high load resistance type incorporates the load resistor formed in the manner as described above. The load resistor shows a maximum resistance value depending upon the phosphorous ion implantation and has a sheet resistance in the order of several hundred M.OMEGA..quadrature.. In order to attain a sufficiently high resistance value, the polysilicon layer should have a greatest possible length-to-width ratio. However, this is definitely an impeding factor working against a greater component density and miniaturization of the SRAM.
Also, because the load resistor is made of the polysilicon layer and is communicated with the direct contact region to the impurity diffusion region, there is always a possibility that impurities diffuse from the silicon substrate into the polysilicon load resistor and/or hydrogen atoms penetrate into the polysilicon during manufacturing process, substantially decreasing the resistance value of the high resistance polysilicon layer.
A passivation layer is formed over the top layer of active layers on the semiconductor substrate as a surface protection against environment of using for a long time. The passivation layer is made of plasma silicon nitride (P-SiN). The plasma silicon nitride contains many hydrogen atoms. Thus, the hydrogen atoms penetrate into the polysilicon layer during both the manufacturing process of passivation layer and a long time for using semiconductor devices. The penetration of hydrogen atoms decreases the resistance value of the high resistance polysilicon layer.
Silicon oxide and/or silicon nitride layers for isolation between active layers are formed over the polysilicon layer under the passivation layer. The isolation layers are formed by using SiH.sub.4 or SiH.sub.2 Cl.sub.2 as material gas of chemical vapor deposition (CVD). For example, hydrogen gas is produced in the manufacturing process of silicon oxide and/or silicon nitride layers as shown in the following reaction formula. EQU SiH.sub.4 +O.sub.2 .fwdarw.SiO.sub.2 +2H.sub.2 EQU 3SiH.sub.4 +4NH.sub.3 .fwdarw.Si.sub.3 N.sub.4 +12H.sub.2
The generated hydrogen gas penetrates into the polysilicon layer. Therefore, the penetration of hydrogen atoms decreases the resistance value of the high resistance polysilicon layer.
In an attempt to provide a smaller SRAM of high load resistance type, it has been proposed to use a load resistor made of an insulating material in Japanese Patent Laying-Open No. 62-195170. A semiconductor device incorporating such load resistor is illustrated in partial cross-section in FIG. 15.
As shown, an electric current path which comprises an N.sup.+ impurity diffusion regions 3 and an aluminum interconnection 8 is provided vertically with respect to the major surface of the P-type silicon substrate 1. Inserted in the electrical path is a load resistor in the form of an insulating oxide layer 65 of transition metal such as Fe.sub.2 O.sub.3, NiO, CoO, TiO.sub.2. A silicon oxide layer 71 and an intervening insulating layer 7 are provided between the metal oxide layer 65 and the P-type silicon substrate 1. The silicon oxide layer 71 is made by thermal oxidation and the intervening insulation layer 7 is made by CVD process.
As stated above, the oxide layer of the transition metal has been employed as the high resistance load resistor in the prior art. However, the oxide layer of the transition metal tends to contaminate the semiconductor substrate during manufacturing of the semiconductor device. In addition, since the conventional load resistor comprises a single oxide layer, the leakage current at the junction in the semiconductor substrate increases, resulting in a greater powerful consumption during the standby. The reason is based on the mechanical stress which locally remains in the oxide layer of the transition metal. The oxide layer of the transition metal may have residual mechanical stress inside the layer caused by the difference between the thermal expansion coefficient of the oxide layer of the transition metal and that of the silicon substrate in the manufacturing process. The mechanical stress may have an influence on the N.sup.+ impurity diffusion regions. The influence causes the increase of the leakage current at the junction in the semiconductor substrate. The single oxide layer construction of the load resistor makes it difficult to control each resistance at a desired value.